The probability that a flaw will occur in a die when manufacturing an integrated circuit (IC) generally increases as the size of the die used to implement the IC increases. The occurrence of a manufacturing flaw, also referred to as a “fault,” within an IC can result in a reduction, or complete failure, in the operability of the IC. For this reason, it can be more cost effective to implement an IC in the form of a multi-die IC as opposed to a single, monolithic die.
A multi-die IC, in general, is formed using a plurality of dies coupled together and disposed within a single package. A manufacturing fault occurring within any one of the dies of a multi-die IC renders only that die inoperable. Thus, within a multi-die IC, a manufacturing fault renders less die area unusable than when a fault occurs within an IC formed of a single, larger die.
While the use of multi-die ICs can increase yield with respect to the final product, multi-die ICs still must undergo thorough testing. For example, the connectivity among the different dies that are combined to form the multi-die IC structure must be robust and reliable. Otherwise, the entire multi-die IC, referring to each constituent die, becomes unusable.